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INTEGRATED CIRCUITS
DATA SHEET
PCF8533 Universal LCD driver for low multiplex rates
Product specification Supersedes data of 1999 Mar 12 File under Integrated Circuits, IC12 1999 Jul 30
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Power-on reset LCD bias generator LCD voltage selector LCD drive mode waveforms Static drive mode 1 : 2 multiplex drive mode 1 : 3 multiplex drive mode 1 : 4 multiplex drive mode Oscillator Internal clock External clock Timing Display register Segment outputs Backplane outputs Display RAM Data pointer Subaddress counter Output bank selector Input bank selector Blinker 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 13 14 15 16 17 18
PCF8533
CHARACTERISTICS OF THE I2C-BUS Bit transfer START and STOP conditions System configuration Acknowledge PCF8533 I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Cascaded operation LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS BONDING PAD LOCATIONS DEVICE PROTECTION TRAY INFORMATION DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS BARE DIE DISCLAIMER
1999 Jul 30
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
1 FEATURES
PCF8533
* Single-chip LCD controller/driver * Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing * Selectable display bias configuration: static, 12 or 13 * Internal LCD bias generation with voltage-follower buffers * 80 segment drives: up to forty 8-segment numeric characters; up to twentyone 15-segment alphanumeric characters; or any graphics of up to 320 elements * 80 x 4-bit RAM for display data storage * Auto-incremented display data loading across device subaddress boundaries * Display memory bank switching in static and duplex drive modes * Versatile blinking modes * LCD and logic supplies may be separated * Wide power supply range: from 1.8 to 5.5 V * Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 6.5 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs * Low power consumption * 400 kHz I2C-bus interface * TTL/CMOS compatible * Compatible with 4-bit, 8-bit or 16-bit microprocessors/microcontrollers * May be cascaded for large LCD applications (up to 5120 segments possible) * No external components * Compatible with Chip-On-Glass (COG) technology * Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8533U - chip with bumps in tray DESCRIPTION VERSION - 2 GENERAL DESCRIPTION
The PCF8533 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCF8533 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes).
1999 Jul 30
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Philips Semiconductors
Universal LCD driver for low multiplex rates
BLOCK DIAGRAM
BP0 BP1 BP2 BP3
S0 to S79
80 VLCD BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS
LCD VOLTAGE SELECTOR
DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT AND BLINK CONTROL
VSS
LCD BIAS GENERATOR
4
CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE OSC OSCILLATOR POWER-ON RESET SCL SDA INPUT FILTERS I2C-BUS CONTROLLER SA0 SDAACK
PCF8533
DISPLAY RAM
COMMAND DECODE
WRITE DATA CONTROL
DATA POINTER AND AUTO INCREMENT
SUBADDRESS COUNTER
MGL743
VDD
A0
A1
A2
Product specification
PCF8533
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
5 PINNING SYMBOL SDAACK SDA SCL CLK VDD SYNC OSC A0, A1 and A2 SA0 VSS VLCD BP0, BP1, BP2 and BP3 S0 to S79 Note 1. For most applications SDA and SDAACK will be shorted together; see Chapter 7. 6 FUNCTIONAL DESCRIPTION PAD 1 2 and 3 4 and 5 6 7 8 9 10, 11 and 12 13 14 15 17, 99, 16 and 98 18 to 97 I2C-bus DESCRIPTION
PCF8533
acknowledge output; note 1
I2C-bus serial data input; note 1 I2C-bus serial clock input external clock input/output supply voltage cascade synchronization input/output internal oscillator enable input subaddress inputs I2C-bus slave address input; bit 0 logic ground LCD supply voltage LCD backplane outputs LCD segment outputs
The PCF8533 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments. The display configurations possible with the PCF8533 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1. All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.2. The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8533. The internal oscillator is selected by connecting pad OSC to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application. Table 1 Selection of display configurations NUMBER OF BACKPLANES 4 3 2 1 SEGMENTS 320 240 160 80 7-SEGMENTS NUMERIC DIGITS 40 30 20 10 INDICATOR SYMBOLS 40 30 20 10 14-SEGMENTS ALPHANUMERIC DOT MATRIX CHARACTERS 20 16 10 5 INDICATOR SYMBOLS 40 16 20 10 320 dots (4 x 80) 240 dots (3 x 80) 160 dots (2 x 80) 80 dots (1 x 80)
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
V handbook, full pagewidth DD R tr 2CB SDAACK VDD SDA SCL OSC VLCD
80 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
LCD PANEL (up to 320 elements)
PCF8533
4 backplanes
A0 VSS
A1
A2
SA0 VSS
MGL744
Fig.2 Typical system configuration.
1999 Jul 30
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.1 Power-on reset
PCF8533
At Power-on the PCF8533 resets to a starting condition as follows: 1. All backplane outputs are set to VLCD. 2. All segment outputs are set to VLCD. 3. The drive mode `1 : 4 multiplex with 13bias' is selected. 4. Blinking is switched off. 5. Input and output bank selectors are reset (as defined in Table 5). 6. The I2C-bus interface is initialized. 7. The data pointer and the subaddress counter are cleared. 8. Display disabled. Data transfers on the I2C-bus should be avoided for 1 ms following Power-on to allow completion of the reset action. 6.2 LCD bias generator
The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VOP and the resulting discrimination ratios (D), are given in Table 2. A practical value for VOP is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VOP > 3Vth. Multiplex drive ratios of 1 : 3 and 1 : 4 with 12bias are possible but the discrimination and hence the contrast ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or 21 ---------- = 1.528 for 1 : 4 multiplex). 3 The advantage of these modes is a reduction of the LCD full-scale voltage VOP as follows: * 1 : 3 multiplex (12bias): V OP = 6 x V off(rms) = 2.449V off(rms)
Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connected between VLCD and VSS. The centre resistor can be switched out of the circuit to provide a 12bias voltage level for the 1 : 2 multiplex configuration. 6.3 LCD voltage selector
* 1 : 4 multiplex (12bias): (4 x 3) V OP = --------------------- = 2.309V off(rms) 3 These compare with VOP = 3Voff(rms) when 13bias is used. Note: VOP = VLCD.
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. Table 2 Preferred LCD drive modes: summary of characteristics NUMBER OF LCD DRIVE MODE BACKPLANES LEVELS static 1:2 1:2 1:3 1:4 1 2 2 3 4 2 3 4 4 4 LCD BIAS CONFIGURATION static
1 1 1 1 2 3 3 3
V off(rms) -----------------V OP 0 0.354 0.333 0.333 0.333
V on(rms) -----------------V OP 1 0.791 0.745 0.638 0.577
V on(rms) D = -----------------V off(rms) 2.236 2.236 1.915 1.732
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.4 6.4.1 LCD drive mode waveforms STATIC DRIVE MODE
PCF8533
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.3.
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Tframe VLCD BP0 VSS VLCD Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD state 1 (on) state 2 (off) LCD segments
state 1
0V
-VLCD VLCD
state 2
0V
-VLCD
(b) Resultant waveforms at LCD segment.
MGL745
Vstate1(t) = Vsn(t) - VBP0(t). Von(rms) = VLCD. Vstate2(t) = Vsn + 1(t) - VBP0(t). Voff(rms) = 0 V.
Fig.3 Static drive mode waveforms.
1999 Jul 30
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.4.2 1 : 2 MULTIPLEX DRIVE MODE
PCF8533
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8533 allows the use of 12bias or 13bias in this mode as shown in Figs 4 and 5.
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Tframe VLCD BP0 VLCD/2 VSS state 1 VLCD BP1 VLCD/2 VSS VLCD Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V -VLCD/2 -VLCD VLCD VLCD/2 state 2 0V -VLCD/2 -VLCD (b) Resultant waveforms at LCD segment.
MGL746
LCD segments
state 2
Vstate1(t) = Vsn(t) - VBP0(t). Von(rms) = 0.791VLCD. Vstate2(t) = Vsn(t) - VBP1(t). Voff(rms) = 0.354VLCD.
Fig.4 Waveforms for the 1 : 2 multiplex drive mode with 12bias.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
handbook, full pagewidth
Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 state 2 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD (b) Resultant waveforms at LCD segment.
MGL747
LCD segments
BP0
state 1 state 2
BP1
Sn
Sn + 1
Vstate1(t) = Vsn(t) - VBP0(t). Von(rms) = 0.745VLCD. Vstate2(t) = Vsn(t) - VBP1(t). Voff(rms) = 0.333VLCD.
Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 13bias.
6.4.3
1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.6. 1999 Jul 30 10
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
handbook, full pagewidth
Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V -VLCD/3 -2VLCD/3 -VLCD state 1 state 2 LCD segments
BP0
BP1
BP2
Sn
Sn + 1
Sn + 2
state 1
(b) Resultant waveforms at LCD segment.
MGL748
Vstate1(t) = Vsn(t) - VBP0(t). Von(rms) = 0.638VLCD. Vstate2(t) = Vsn(t) - VBP1(t). Voff(rms) = 0.333VLCD.
Fig.6 Waveforms for the 1 : 3 multiplex drive mode.
6.4.4
1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.7. 1999 Jul 30 11
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
handbook, full pagewidth
Tframe VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 state 1 state 2 LCD segments
BP0
BP1
BP2
BP3
Sn
Sn + 1
Sn + 2
Sn + 3
state 1
state 2
0V -VLCD/3 -2VLCD/3 -VLCD
(b) Resultant waveforms at LCD segment.
MGL749
Vstate1(t) = Vsn(t) - VBP0(t): Von(rms) = 0.577VLCD. Vstate2(t) = Vsn(t) - VBP1(t): Voff(rms) = 0.333VLCD.
Fig.7 Waveforms for the 1 : 4 multiplex drive mode.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.5 6.5.1 Oscillator INTERNAL CLOCK 6.8 Segment outputs
PCF8533
The internal logic and the LCD drive signals of the PCF8533 are timed either by the built-in oscillator or from an external clock. When the internal oscillator is used, pad OSC should be connected to VSS. In this event, the output from pad CLK provides the clock signal for cascaded PCF8533s in the system. After power-up, SDA must be HIGH to guarantee that the clock starts. 6.5.2 EXTERNAL CLOCK
The LCD drive section includes 80 segment outputs (S0 to S79) which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display latch. When less than 80 segment outputs are required the unused segment outputs should be left open-circuit. 6.9 Backplane outputs
The condition for external clock is made by tying pad OSC to VDD; pad CLK then becomes the external clock input. The clock frequency (fCLK) determines the LCD frame frequency. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 6.6 Timing
The timing of the PCF8533 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between the PCF8533s in the system. The timing also generates the LCD frame frequency which it derives as an integer division of the clock frequency (see Table 3). The frame frequency is a fixed division of the internal clock or of the frequency applied to pad CLK when an external clock is used. 6.7 Display register
The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 6.10 Display RAM
The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM.
The display RAM is a static 80 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 80 segments operated with respect to backplane BP0 (see Fig.8). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
When display data is transmitted to the PCF8533 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current mux mode data is stored singularly, in pairs, triplets or quadruplets. e.g. in 1 : 2 mux mode the RAM data is stored every second bit. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.9; the RAM filling organization depicted applies equally to other LCD types. With reference to Fig.9, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses.
PCF8533
In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. Table 3 LCD frame frequencies NOMINAL FRAME FREQUENCY (Hz) 64
FRAME FREQUENCY f CLK ---------24
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display RAM addresses (rows) / segment outputs (S) 0 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3
MGL750
1
2
3
4
75
76
77
78
79
Fig.8
Display RAM bit map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
6.11 Data pointer 6.13 Output bank selector
PCF8533
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored starting at the display RAM address indicated by the data pointer thereby observing the filling order shown in Fig.9. The data pointer is automatically incremented in accordance with the chosen LCD configuration. That is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode). If an I2C-bus data access is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further RAM accesses. 6.12 Subaddress counter
The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. In 1 : 4 multiplex, all RAM addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex, bits 0 and 1 are selected and, in the static mode, bit 0 is selected. The SYNC signal will reset these sequences to the following starting points; bit 3 for 1 : 4 multiplex, bit 2 for 1 : 3 multiplex, bit 1 for 1 : 2 multiplex and bit 0 for static mode. The PCF8533 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 6.14 Input bank selector
The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8533 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 27th display data byte transmitted in 1 : 3 multiplex mode). The hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface.
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
the BANK SELECT command. The input bank selector functions independently to the output bank selector. 6.15 Blinker
PCF8533
The display blinking capabilities of the PCF8533 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating, see Table 4.
An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1 : 2 LCD drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the BLINK command. In the 1 : 3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals.
If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit E at the required rate using the MODE SET command. Table 4 Blinking frequencies BLINKING MODE Off 2 Hz 1 Hz 0.5 Hz NORMAL OPERATING MODE RATIO - f CLK ---------768 f CLK -----------1536 f CLK -----------3072 NOMINAL BLINKING FREQUENCY blinking off 2 Hz 1 Hz 0.5 Hz
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1:3 multiplex 1:4 multiplex
Sn 1
Philips Semiconductors
Universal LCD driver for low multiplex rates
drive mode
LCD segments
a f g e d Sn 6 c b Sn Sn Sn 7 DP 1
LCD backplanes
display RAM filling order
transmitted display byte
Sn Sn Sn
2 3 4 5
BP0
n bit/ BP 0 1 2 3 c x x x
n1 b x x x
n2 a x x x
n3 f x x x
n4 g x x x
n5 e x x x
n6 d x x x
n7 MSB DP x x x cbaf LSB g e d DP
static
Sn
Sn
BP0 a f g b
n bit/ BP
BP1 c
n1 f g x x
n2 e c x x
n3 d DP x x MSB abf LSB g e c d DP
1:2
Sn
1
multiplex
Sn Sn Sn Sn
2 3
e d
DP
0 1 2 3
a b x x
1 2 f
a b g e d c DP Sn
BP0
n bit/ BP
BP1 BP2
n1 a d g x
n2 f e x x MSB b DP c a d g f LSB e
0 1 2 3
b DP c x
Sn f
a b g e d c DP BP1 BP3 BP0 BP2
n bit/ BP 0 1 2 3 a c b DP
n1 f e g d
MSB a c b DP f
LSB egd
Product specification
handbook, full pagewidth
MGL751
PCF8533
X = data bit unchanged.
Fig.9 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
7 CHARACTERISTICS OF THE I2C-BUS 7.4 Acknowledge
PCF8533
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting SDAACK to SDA on the PCF8533, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF8533 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAACK pad to the system SDA line to guarantee a valid low level. The following definition assumes SDA and SDAACK are connected and refers to the pair as SDA. 7.1 Bit transfer
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Fig.13. 7.5 PCF8533 I2C-bus controller
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.10. 7.2 START and STOP conditions
The PCF8533 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8533 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device application, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. 7.6 Input filters
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.11. 7.3 System configuration
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. The system configuration is illustrated in Fig.12.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
7.7 I2C-bus protocol
PCF8533
Two I2C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8533. The least significant bit of the slave address that a PCF8533 will respond to is defined by the level tied at its input SA0. The PCF8533 is a write only device and will not respond to a read access. Therefore, two types of PCF8533 can be distinguished on the same I2C-bus which allows: 1. Up to 16 PCF8533s on the same I2C-bus for very large LCD applications 2. The use of two types of LCD multiplex on the same I2C-bus. The I2C-bus protocol is shown in Fig.14. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8533 slave addresses available. All PCF8533s with the corresponding SA0 level acknowledge in parallel to the slave address, but all PCF8533s with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, a control byte follows which defines if the next byte is RAM or command information. The control byte also defines if the next following byte is a control byte or further RAM/command data.
In this way it is possible to configure the device then fill the display RAM with little overhead. The command bytes and control bytes are also acknowledged by all addressed PCF8533s connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data is directed to the intended PCF8533 device. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8533. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART an I2C-bus access. 7.8 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The five commands available to the PCF8533 are defined in Table 5.
SDA
SCL data line stable; data valid change of data allowed
MBA607
Fig.10 Bit transfer.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.11 Definition of START and STOP conditions.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.12 System configuration.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.13 Acknowledgement on the I2C-bus.
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Universal LCD driver for low multiplex rates
R/W = 0 slave address control byte RAM/command byte M AS B L SP B S S 0 1 1 1 0 0 A 0 A Co RS 0
EXAMPLES a) transmit two bytes of RAM data S S011100A0A01 0 A RAM DATA A RAM DATA AP
b) transmit two command bytes S S011100A0A10 0 A COMMAND A00 A COMMAND AP
c) transmit one command byte and two RAM bytes S S011100A0A10 0 A COMMAND A01 A RAM DATA A RAM DATA AP
MGL752
Fig.14 I2C-bus protocol.
MSB Co RS UNUSED
LSB
Product specification
Co = 0; last control byte. Co = 1; control bytes continue. RS = 0; data is a command byte RS = 1; data is a display byte
MGL753
PCF8533
Fig.15 Format of control byte.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
Table 5 Definition of PCF8533 commands OPCODE 1 1 0 0 E B M1 OPTIONS M0 Table 6 Table 7 Table 8
PCF8533
COMMAND MODE SET
DESCRIPTION defines LCD drive mode defines LCD bias configuration defines display status; the possibility to disable the display allows implementation of blinking under external control seven bits of immediate data, bits P6 to P0, are transferred to the data pointer to define one of eighty display RAM addresses three bits of immediate data, bits A0 to A3, are transferred to the subaddress counter to define one of eight hardware subaddresses defines input bank selection (storage of arriving display data) defines output bank selection (retrieval of LCD display data); the BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes defines the blinking frequency selects the blinking mode; normal operation with frequency set by BF1, BF0 or blinking by alternation of display RAM banks. Alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes
LOAD DATA POINTER DEVICE SELECT BANK SELECT
0
P6
P5
P4
P3
P2
P1
P0
Table 9
1
1
1
0
0
A2
A1
A0
Table 10
1
1
1
1
1
0
I
O
Table 11 Table 12
BLINK
1
1
1
1
0
A
BF 1
BF Table 13 0 Table 14
Table 6
Mode set option 1 LCD DRIVE MODE DRIVE MODE Static 1:2 1:3 1:4 BACKPLANE 1 BP MUX (2 BP) MUX (3 BP) MUX (4 BP) M1 0 1 1 0 BITS M0 1 0 1 0
Table 7
Mode set option 2 LCD BIAS
1 1 3bias 2bias
BIT B 0 1
Table 8
Mode set option 3 DISPLAY STATUS BIT E 0 1
Disabled (blank) Enabled
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
Table 9 Load data pointer option 1 BITS P6 P5 P4 P3 P2 P1 P0 7.10 Cascaded operation
PCF8533
DESCRIPTION 7 bit binary value of 0 to 79
Table 10 Device select option 1 DESCRIPTION 3 bit binary value of 0 to 7 Table 11 Bank select option 1 (Input) STATIC RAM bit 0 RAM bit 2 1 : 2 MUX RAM bits 0 and 1 RAM bits 2 and 3 BIT I 0 1 A2 BITS A1 A0
In large display configurations, up to 16 PCF8533s can be distinguished on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). When cascaded PCF8533s are synchronized they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8533s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Fig.16). The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8533s. This synchronization is guaranteed after the Power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCF8533s with different SA0 levels are cascaded). SYNC is organized as an input/output pad; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCF8533 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF8533 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8533 are shown in Fig.17. The contact resistance between the SYNC pads of cascaded devices must be controlled. If the resistance is too high then the device will not be able to synchronize properly. This is particularly applicable to COG applications. Table 15 shows the limiting values for contact resistance. Table 15 SYNC contact resistance NUMBER OF DEVICES 2 3 to 5 6 to 10 11 to 16 MAXIMUM CONTACT RESISTANCE 6000 2200 1200 700
Table 12 Bank select option 2 (Output) STATIC RAM bit 0 RAM bit 2 1 : 2 MUX RAM bits 0 and 1 RAM bits 2 and 3 BIT O 0 1
Table 13 Blink option 1 BITS BLINK FREQUENCY BF1 Off 2 Hz 1 Hz 0.5 Hz Table 14 Blink option 2 BLINK MODE Normal blinking(1) Alternation blinking Note 1. Normal blinking is assumed when multiplex rates 1 : 3 or 1 : 4 are selected. 7.9 Display controller BIT A 0 1 0 0 1 1 BF0 0 1 0 1
The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8533 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
handbook, full pagewidth
SDAACK VDD SDA SCL SYNC CLK OSC A0 VLCD VDD tr 2CB SDAACK VDD SDA SCL SYNC CLK OSC VLCD
80 segment drives 80 segment drives
VLCD
PCF8533
BP0 to BP3 (open-circuit)
LCD PANEL (up to 5120 elements)
A1
A2
SA0 VSS
R
HOST MICROPROCESSOR/ MICROCONTROLLER
PCF8533
4 backplanes
BP0 to BP3
MGL754
VSS
A0
A1
A2
SA0 VSS
Fig.16 Cascaded PCF8533 configuration.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
handbook, full pagewidth
1 Tframe = f frame
BP0
SYNC (a) static drive mode. BP1 (1/2 bias)
BP1 (1/3 bias)
SYNC (b) 1 : 2 multiplex drive mode.
BP2
SYNC (c) 1 : 3 multiplex drive mode.
BP3
SYNC
MGL755
(d) 1 : 4 multiplex drive mode.
Fig.17 Synchronization of the cascade for the various PCF8533 drive modes.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD IDD VLCD ILCD ISS VI(n) VO(n) II IO Ptot P/out Tstg 9 HANDLING supply voltage supply current LCD supply voltage LCD supply current negative supply current input voltage on pads SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2 output voltage on pads S0 to S79 and BP0 to BP3 DC input current DC output current total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 -50 VSS - 0.5 -50 -50 VSS - 0.5 VSS - 0.5 -10 -10 - - -65
PCF8533
MAX. +6.5 +50 +7.5 +50 +50 VDD + 0.5 VLCD + 0.5 +10 +10 400 100 +150 V
UNIT mA V mA mA V V mA mA mW mW C
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices" ).
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
10 DC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD ILCD Logic VIL VIH IOL1 IOH1 IOL2 IL1 IL2 VPOR CI VBP VS RBP RS Notes LOW-level input voltage HIGH-level input voltage LOW-level output current on pads CLK and SYNC HIGH-level output current pad CLK LOW-level output current pad SDA leakage current on pads SA0, A0 to A2, CLK, SDA and SCL leakage current pad OSC Power-on reset voltage level input capacitance note 2 VSS 0.7VDD VOL = 0.4 V; VDD = 5 V 1 VOH = 4.6 V; VDD = 5 V VI = VDD or VSS VI = VDD -1 - - - - - - - 1.3 - - - 1.5 6.0 supply voltage LCD supply voltage supply current LCD supply current 1.8 2.5 fCLK = 1536 Hz; note 1 - fCLK = 1536 Hz; note 1 - - - 8 24 5.5 6.5 20 60 PARAMETER CONDITIONS MIN. TYP.
PCF8533
MAX.
UNIT
V V A A V V mA mA mA A A V pF
0.3VDD VDD - - - +1 +1 1.6 7
VOL = 0.4 V; VDD = 5 V 3 -1 -1 1.0 - -100 -100 - -
LCD outputs DC voltage component on pads BP0 to BP3 DC voltage component on pads S0 to S79 output resistance at pads S0 to S79 CBP = 35 nF CS = 5 nF +100 +100 10 13.5 mV mV k k
output resistance at pads BP0 to BP3 VLCD = 5 V; note 3 VLCD = 5 V; note 3
1. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 2. Not tested; given by design. 3. Outputs measured one at a time.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
11 AC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = -40 to + 85 C; unless otherwise specified. SYMBOL fCLK tCLKH tCLKL td(p)SYNC tSYNCL td(PLCD) PARAMETER oscillator frequency at pad CLK input CLK HIGH time input CLK LOW time SYNC propagation delay time SYNC LOW time driver delays with test loads VLCD = 5 V CONDITIONS VDD = 5 V; note 1 MIN. 797 130 130 - 1 - - 1.3 0.6 0.6 1.3 0.6 - - - 100 0 0.6 - TYP. 1536 - - 30 - - - - - - - - - - - - - - -
PCF8533
MAX. 3046 - - - - 30
UNIT Hz s s ns s s
Timing characteristics: I2C-bus; note 2 fSCL tBUF tHD;STA tSU;STA tLOW tHIGH tr tf Cb tSU;DAT tHD;DAT tSU;STO tSW Notes 1. Typical output duty cycle of 50%. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SCL clock frequency bus free time between a STOP and START START condition hold time set-up time for a repeated START condition SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time capacitive bus line load data set-up time data hold time set-up time for STOP condition tolerable spike width on bus 400 - - - - - 0.3 0.3 400 - - - 50 kHz s s s s s s s pF ns ns s ns
handbook, full pagewidth
SYNC
6.8 (2%) 3.3 k (2%)
VDD
CLK
0.5VDD
SDA, SCL
1.5 k (2%)
VDD
BP0 to BP3, and S0 to S79
1 nF VSS
MGS120
Fig.18 Test loads.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
handbook, full pagewidth
1/ fCLK tCLKH tCLKL 0.7VDD 0.3VDD
CLK
SYNC
0.7VDD 0.3VDD td(p)(SYNC) tSYNCL 0.5 V td(p)(SYNC)
BP0 to BP3, and S0 to S79
(VDD = 5 V) 0.5 V tPLCD
MGL761
Fig.19 Driver timing waveforms.
dbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t
HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.20 I2C-bus timing waveforms.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
12 BONDING PAD LOCATIONS Bonding pad locations (dimensions in m) All x and y coordinates are referenced to centre of chip (see Fig.22). SYMBOL SDAACK SDA SDA SCL SCL CLK VDD SYNC OSC A0 A1 A2 SA0 VSS VLCD BP2 BP0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 1999 Jul 30 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 x -1079.20 -839.20 -759.20 -599.20 -519.20 -414.80 -284.80 +4.20 +119.20 +249.20 +379.20 +581.20 +711.20 +841.20 +1099.60 +1277.60 +1357.60 +1437.60 +1517.60 +1597.60 +1677.60 +1757.60 +1837.60 +1917.60 +1997.60 +2077.60 +2157.60 +2237.60 +2317.60 +2357.60 +2277.60 +2197.60 +2117.60 +2037.60 +1957.60 +1877.60 +1797.60 y -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 30 SYMBOL S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 PAD 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 x
PCF8533
y +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40
+1717.60 +1637.60 +1557.60 +1477.60 +1317.60 +1237.60 +1157.60 +1077.60 +997.60 +917.60 +837.60 +757.60 +677.60 +597.60 +437.60 +357.60 +277.60 +197.60 +117.60 +37.60 -42.40 -122.40 -202.40 -282.40 -362.40 -442.40 -602.40 -682.40 -762.40 -842.40 -922.40 -1002.40 -1082.40 -1162.40 -1242.40 -1322.40 -1402.40
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
PCF8533
SYMBOL S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78
PAD 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
x -1562.40 -1642.40 -1722.40 -1802.40 -1882.40 -1962.40 -2042.40 -2122.40 -2202.40 -2282.40 -2362.40 -2322.40 -2242.40 -2162.40 -2082.40 -2002.40 -1922.40 -1842.40 -1762.40 -1682.40 -1602.40 -1522.40
y +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 +594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40 -594.40
SYMBOL S79 BP3 BP1 Alignment marks C1 C2 F
PAD 97 98 99 - - - (S11) (S11) (S12) (S12) (S67) (S67) (S68) (S68) - -
x -1442.40 -1362.40 -1282.40 +2300.5 -2320.2 -2208.3 +2469.70 +2549.70 +2517.60 +2437.60 -2442.30 -2522.30 -2554.40 -2474.40 -2695.00 +2695.00
y -594.40 -594.40 -594.40 +55.0 +107.0 -165.4 -594.40 -594.40 +594.40 +594.40 +594.40 +594.40 -594.40 -594.40 -750.00 +750.00
Dummy pads (connected to segments shown; note D1 D2 D3 D4 D5 D6 D7 D8
Chip corners (pre-sawing) Bottom left Top right Note 1. The dummy pads are not tested.
handbook, halfpage
REF
C2
REF
C1
MGL756
F
REF
Fig.21 Alignment markers.
1999 Jul 30
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ok, full pagewidth
D6 D5 S67
PC8533-2
y
C2 F
32
SDA SCL CLK VDD SYNC OSC SA0 SDAACK VSS S79 BP3 BP1 BP2 BP0 S0 S1 S2 A0 A1 D7 D8 S68 A2 VLCD 0, 0 x
C1
S11 D1 D2
S12 D4 D3
1999 Jul 30
The position of the bonding pads is not to scale. Chip dimensions: approximately 5.40 x 1.51 mm. Bump dimensions: 90 x 50 x 17.5 m. Wafer thickness: 381 m.
Philips Semiconductors
Universal LCD driver for low multiplex rates
. . . . . . . . . . . .
Fig.22 Bonding pad locations.
. . .
. . .
MGL759
Product specification
PCF8533
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
13 DEVICE PROTECTION
PCF8533
handbook, full pagewidth
VDD SA0
VDD
VSS VDD CLK
VSS
SCL VSS VDD VSS OSC
VSS VDD SYNC SDA
VSS VDD A0, A1 A2
VSS
SDAACK VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD S0 to S79 VSS VLCD VSS
VSS
MGL760
Fig.23 Device protection diagram.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
14 TRAY INFORMATION
PCF8533
handbook, full pagewidth
x
A
C
y D
B F
E
MGL757
The dimensions are given in Table 16.
Fig.24 Tray details.
Table 16 Dimensions DIM. A B
handbook, halfpage
DESCRIPTION pocket pitch, x direction pocket pitch, y direction pocket width, x direction pocket width, y direction tray width, x direction tray width, y direction no. pockets in x direction no. pockets in y direction
VALUE 7.37 mm 3.68 mm 5.50 mm 1.60 mm 50.8 mm 50.8 mm 6 12
C D E F x
PC8533-2
y
MGL758
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface.
Fig.25 Tray alignment.
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Philips Semiconductors
Product specification
Universal LCD driver for low multiplex rates
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8533
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
18 BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
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Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 67
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/02/pp36
Date of release: 1999
Jul 30
Document order number:
9397 750 05045

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